Use of a U-groove as an alternative to using a V-groove for protection against dicing induced damage in silicon

ABSTRACT

The present disclosure relates that by modifying chip die dicing methodology to a U-groove profile from a V-groove profile by modifying the second etch step to be a dry etch instead of a wet etch results in a direct cost savings by eliminating a more expensive process step, as well as the need for stripping the developed photoresist layer. Furthermore, going to a U-groove profile accomplishes additional indirect and greater cost savings resulting from increased process throughput, improved yield, and reduced metal layer defects.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of U.S. appln. Ser. No. 09/996,681 filed Nov. 30,2001 by the same inventors, and claims priority therefrom. Thisdivisional application is being filed in response to a restrictionrequirement in that prior application and contains re-written and/oradditional claims to the restricted subject matter.

BACKGROUND OF THE INVENTION AND MATERIAL DISCLOSURE STATEMENT

The present invention relates generally to the fabrication ofsemiconductor devices. In particular, to the dicing of integratedcircuit chips with great accuracy, and within close proximity tofabricated elements on the chip. The invention relates, mostparticularly, to the dicing of silicon sensor chips as employed fordigital image sensors.

Image sensor dies for scanning document images, such as Charge CoupledDevices (CCDs), typically have a row or linear array of photo-sitestogether with suitable supporting circuitry integrated onto silicon.Usually, a die of this type is used to scan line by line across thewidth of a document with the document being moved or stepped lengthwisein synchronism therewith.

In the above application, the image resolution is proportional to theratio of the scan width and the number of array photo-sites. Because ofthe difficulty in economically designing and fabricating long dies,image resolution for the typical die commercially available today isrelatively low when the die is used to scan a full line. Whileresolution may be improved electronically as by interpolating extraimage signals, or by interlacing several smaller dies with one anotherin a non-collinear fashion so as to crossover from one die to the nextas scanning along the line progresses, electronic manipulations of thistype adds to both the complexity and the cost of the system. Further,single or multiple die combinations such as described above usuallyrequire more complex and expensive optical systems.

However, a long or full width array, having a length equal to or largerthan the document line and with a large packing of co-linear photo-sitesto assure high resolution, has been and remains a very desirablearrangement. In the pursuit of a long or full width array, forming thearray by assembling several small dies together end to end has become anexemplary arrangement. However, this necessitates providing dies whosephoto-sites extend to the border or edge of the die, so as to assurecontinuity when the die is assembled end to end with other dies, and atthe same time provide edges that are sufficiently smooth and straight tobe assembled together without loss of image data.

Although the standard technique of scribing and cleaving silicon wafersused by the semiconductor industry for many years produces dies havingreasonably controlled dimensions, the microscopic damage occurring tothe die surface during the scribing operation has effectively precludedthe disposition of the photo-sites at the die edge. This is because thetop surface of silicon wafers is virtually always parallel to the <100>plane of the crystalline lattice so that, when a wafer of this type iscut or diced with a high speed diamond blade, chips and slivers arebroken away from the top surface of the wafer in the direct vicinity ofthe channel created by the blade. This surface chipping typicallyextends to about 50 microns, thus, rendering it impossible for activeelements to be located any closer than about 50 microns from the dicingchannel. This as a result, has driven the adoption of V-shaped groovesas a technique for providing much smoother dicing and thereby enabledtighter dicing accuracy and closer proximity of active chip elements tothe chip/die edge.

U.S. Pat. No. 4,814,296 discloses a process for forming individual dieshaving faces that allow the dies to be assembled against other like diesto form one and/or two dimensional scanning arrays wherein the activeside of a wafer is etched to form small V-shaped grooves defining thedie faces, relatively wide grooves are cut in the inactive side of thewafer opposite each V-shaped groove, and the wafer cut by sawing alongthe V-shaped grooves, the saw being located so that the side of the sawblade facing the die is aligned with the bottom of the V-shaped grooveso that there is retained intact one side of the V-shaped groove tointercept and prevent cracks and chipping caused by sawing from damagingthe die active surface and any circuits thereon. U.S. Pat. No. 4,814,296is hereby incorporated by reference in its entirety for its teaching.

However, utilization of a V-shaped groove technique while effective hasproven to be expensive. This expense may be broadly characterized as dueprimarily to two things. Both of these arise from the requirement for ananisotropic etch so as to maintain a V-groove wall which is parallel tothe <111> crystalline plane found in the wafer. First, there are theextra foundry costs. An anisotropic etch is a wet etch and as such is anon-standard process for most silicon foundries. This also means thatthe wafers must be stripped of their photoresist and require extrahandling with placement in an off-line wet etch tool as well. Secondly,there is the cost impact resulting from chip yield effects. Anisotropicetching is by nature an aggressive etch due to the chemicals employedand, thus, often attacks and damages the top layers of passivation oxideand metal on the wafer. This is further exacerbated by the stripping ofthe photoresist, which would otherwise act as a barrier layer and aid inpreventing wafer damage.

Therefore, as discussed above, there exists a need for an arrangementand methodology which will solve the problem of preventing cracks andchipping caused by damage from sawing while minimizing the costs ofdoing so. Thus, it would be desirable to solve this and otherdeficiencies and disadvantages as discussed above with an improvedsemiconductor dicing methodology.

The present invention relates to a method for dicing die from asemiconductor wafer while allowing a very close cut of a die edgerelative to active elements on the die without damaging the activeelements. The method steps comprise etching a U-groove via a dry etch inthe semiconductor wafer and sawing the semiconductor wafer along theU-groove where one edge of the saw is substantially in alignment withthe bottom of the U-groove.

In particular, the present invention relates to a method for dicing diefrom a semiconductor wafer while allowing a very close cut of a die edgerelative to active elements on the die without damaging the activeelements. The method steps comprising etching by way of a first dry etchan opening down to the surface of the semiconductor wafer, followed byetching by way of a second dry etch a U-groove in the opening down tothe surface of the semiconductor wafer created by the first dry etch,and then sawing the semiconductor wafer along the U-groove where oneedge of the saw is substantially in alignment with the bottom of theU-groove.

The present invention also relates to a method of fabricating highresolution image sensor dies from a wafer so that the dies haveprecision faces to enable the dies to be assembled with other like diesto form a larger array without image loss or distortion at the pointswhere the dies are assembled together. The method comprising the stepsof etching small U-shaped grooves in one side of a wafer delineating thefaces of the dies where the dies are to be separated from the wafer.This is followed by forming grooves in the opposite side of the waferopposite each of the U-shaped grooves, the axis of the grooves beingparallel to the axis of the U-shaped groove opposite thereto. In turnthis is followed by, sawing the wafer along the U-shaped grooves withone side of the cut made by sawing being substantially coextensive withthe bottom of the U-shaped grooves whereby one side of the U-shapedgrooves is at least partially obliterated by the sawing, the sides ofthe U-shaped grooves that remain serving to prevent development offractures in the die beyond the remaining side as the wafer is beingsawed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a cross section of the wafer at the dicing channel and atthat process step where a groove is to be cut prior to the wet etch.

FIG. 2 depicts the result after formation of a V-groove.

FIG. 3 depicts the result after formation of a U-groove.

FIG. 4 depicts the schematical representation of both a V-groove and anU-groove for purposes of geometric comparison.

DESCRIPTION OF THE INVENTION

The prior approach employed of using a V-groove for dicing image sensordies as described above has associated with it increased costs, processcycle time, reduced yield and increased metal layer defects. Thedisclosure taught herein overcomes these disadvantages by replacing theV-groove with a U-groove, using in one embodiment a dry etch consistingof SF₆, He and O₂. The intent of etching a V-groove into the silicon isto relieve damage to the device caused by dicing the wafer. A U-groovehas proven itself as an improvement because the angle of the U-groove issufficient to deflect cracking and stress away from the device whileonly requiring a dry etch for its achievement.

FIG. 1 depicts a cross section of a wafer 100 comprising dies to bediced. The cross section depicted is a SEM magnification of one dicingchannel on wafer 100. Here in FIG. 1 is depicted the result afterphotoresist 101 has been applied, exposed, and developed, and with asubsequent first dry etch performed to etch through any metal layers 102as well as any TEOS 103 (Tetraethylorthosilicate) layers to reach thesilicon surface 104 of the silicon layer 105. This opens oxide opening104 to about 6 microns in width in one preferred embodiment. Thephotoresist 101, at initially 22000 angstroms, is attacked by the firstdry etch at a rate of about 52 angstroms per second, leavingapproximately 5000 angstroms behind.

In FIG. 2 there is depicted the result for a prior art V-groove process.The photoresist of FIG. 1 has been stripped away and the wafertransferred to a wet etch tool for a Tetra methyl Ammonium Hydroxide(TMAH) wet etch of 330 seconds. This TMAH etch has been favored for itsanisotropic etching effect, however it also attacks the final-levelmetal through cracks in the TEOS passivation layers impacting chipyield. In one typical embodiment, the V-groove 200 that results for anapproximate 6 micron opening will have an approximate depth of 4 micronsand a total width with undercut of about 7.5 microns as typified in thedepiction provided in FIG. 2.

The U-groove 300 is depicted in FIG. 3. The U-groove process begins thesame as the V-groove process. However, it departs in its process stepssubsequent to the stage depicted in FIG. 1. Unlike with the V-grooveprocess, whatever remains of the photoresist 101 is not stripped. Thephotoresist 101 is left in place thereby eliminating the stripping stepand by virtue of retaining the photoresist 101 it also further providesprotection for the underlying metal and TEOS layers in the followingsteps.

The next step in the methodology is to employ a second dry etchconsisting of SF6 and O2, and thereby create the U-groove 300 in siliconlayer 105 as shown in FIG. 3. The original intent of etching a V-Groove200 into the silicon 105 is to relieve damage to the die caused bydicing the wafer. A U-Groove 300 is an acceptable alternative becausethe angle of the groove is sufficient to deflect cracking and stressaway from any devices on the wafer 100. Replacing the V-Groove 200 witha U-Groove 300 results in cost savings, increased process throughput,improved yield and reduced metal-3 defects, all by virtue of eliminatingthe wet TMAH etch.

Table (1) shows parameter range median start points developed for oneU-Groove 300 embodiment. It will be well understood by those skilled inthe art that these parameters will vary from tool to tool, and that itis not useful to provide greater specifics. It will also be understoodthat these parameters may be varied even upon the same tool, yet stillachieve the same results. Nevertheless, etching silicon is wellunderstood in the art, and those so skilled will be able with the tableto practice the invention without undue experimentation. The reportedetch time in the table of about 75 seconds was needed for a 4 microndeep U-Groove 300, which is also the approximate depth of the V-Groove200 in one preferred embodiment. TABLE 1 U-Groove Etch Parameters for aDry Etch Tool Parameter Median Start Points Pressure Approximately 300mTorr RF Approximately 200 Watts O₂ Flow Approximately 15 sccm He FlowApproximately 65 sccm SF₆ Flow Approximately 175 sccm Etch TimeApproximately 75 seconds

A schematic profile of a V-Groove and U-Groove is shown in FIG. 4 forcomparison and to clarify the target dimensions. The desired U-Groove300 dimensions were derived from the specifications and requirements setfor V-Grooves and by the limitations in the U-Groove etch process. Theminimum V-Groove 200 depth is 3.5 microns and 7.5 microns wide, with anoxide opening of 6.0 microns and flat bottom less than 1 microns.U-Groove 300 specifications will be targeted to 4.5±1 microns for boththe oxide opening and depth, with a U-Groove 300 width between 6.2microns and 9.7 microns. The desired variation in depth across the waferis less than 15 percent. In achieving this, the U-Groove 300 oxideopening is best made significantly smaller than the correspondingV-Groove oxide opening to help reduce the overall U-Groove width.However, this is not a requirement to practice the invention.Substituting a new V-Groove mask is, therefore, used in one embodimentto achieve an oxide opening of 4.5 microns for the U-Groove process.

The subsequent steps for dicing the wafer into die are as is well knownby those skilled in the art, and also as described in U.S. Pat. No.4,814,296 previously incorporated above. A second groove is formed inthe bottom or inactive surface of the wafer 100 opposite and parallel toeach U-groove 300. The wafers are then typically secured and cut using asuitable cutting device such as a high speed diamond dicing blade.

In closing, by going to a U-groove profile and modifying the second etchto be a dry etch instead of a wet etch results in a direct cost savingsby eliminating a more expensive process step, as well as the need forstripping the developed photoresist layer. Furthermore, going to aU-groove profile accomplishes additional indirect and perhaps greatercost savings from the increased process throughput, improved yield, andreduced metal layer defects.

While the embodiments disclosed herein are preferred, it will beappreciated from this teaching that various alternative, modifications,variations or improvements therein may be made by those skilled in theart. For example, it will be understood by those skilled in the art thatthe teachings provided herein may be applicable to other semiconductortypes, including: gallium arsenide, and particularly to silicon oninsulator, and amorphous silicon. There are also many other tool setsknown to those skilled in the art with which to effectively provide asuitable dry etch as well as other combinations of etch rate, pressure,RF energy, gas rate, and etch time beyond those disclosed. All suchvariants of processing technique are intended to be encompassed by thefollowing claims:

1. A method for dicing die from a semiconductor wafer while allowing avery close cut of a die edge relative to active elements on the diewithout damaging the active elements comprising: etching a U-groove viaa dry etch in the semiconductor wafer; and sawing the semiconductorwafer along the U-groove where one edge of the saw is substantially inalignment with the bottom of the U-groove.
 2. The method of claim 1wherein the dry etch uses a combination of gases comprising SF₆ and O₂.3. The method of claim 2 wherein the semiconductor wafer is comprised ofamorphous silicon.
 4. The method of claim 2 wherein the semiconductorwafer is comprised of gallium arsenide
 5. The method of claim 2 whereinthe semiconductor wafer is comprised of a III-V compound.
 6. The methodof claim 2 wherein the semiconductor wafer is comprised of silicon oninsulator.
 7. The method of claim 2 wherein the U-groove isapproximately 4 microns in depth.
 8. The method of claim 2 wherein theU-groove is approximately 3.5 to 5.5 microns in depth.
 9. The method ofclaim 7 wherein the U-groove is approximately 6 to 10 microns in width.10. A method for dicing die from a semiconductor wafer while allowing avery close cut of a die edge relative to active elements on the diewithout damaging the active elements comprising: etching a U-grooveapproximately 3.5 to 5.5 microns in depth via a dry etch in thesemiconductor wafer; and sawing the semiconductor wafer along theU-groove where one edge of the saw is substantially in alignment withthe bottom of the U-groove.
 11. The method of claim 10 wherein the dryetch uses a combination of gases comprising SF₆ and O₂.
 12. The methodof claim 10 wherein the semiconductor wafer is comprised of amorphoussilicon.
 13. The method of claim 10 wherein the semiconductor wafer iscomprised of gallium arsenide
 14. The method of claim 10 wherein thesemiconductor wafer is comprised of a III-V compound.
 15. The method ofclaim 10 wherein the semiconductor wafer is comprised of silicon oninsulator.
 16. The method of claim 10 wherein the U-groove isapproximately 4 microns in depth.
 17. The method of claim 10 wherein theU-groove is approximately 6 to 10 microns in width.